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Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV.
There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
Chuan Seng Tan, Kuan-Neng Chen
3D Integration Technology - Introduction and Overview. A Systems Perspective on 3D Integration: What is 3D? And What is 3D Good For? Wafer Bonding Techniques. TSV Etching. TSV Filling. 3D Technology Platform: Temporary Bonding and Release. 3D Technology Platform: Wafer Thinning, Stress Relief, and Thin Wafer Handling. Advanced Die-to-Wafer 3D Integration Platform: Self-Assembly Technology. Advanced Direct Bond Technology. Surface Modification Bonding at Low Temperature for Three-Dimensional Hetero-Integration. Through Silicon Via Implementation in CMOS Image Sensor Product. A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through- Silicon Via and Hybrid Cu-Adhesive Bonding. Power Delivery in 3D IC Technology with a Stratum Having an Array of Monolithic DC-DC Point-of-Load (PoL) Converter Cells. Thermal-Aware 3D IC Designs. 3D IC Design Automation Considering Dynamic Power and Thermal Integrity. Outlook.
