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This self-contained tutorial comprehensively discusses the analysis and synthesis of both synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995. The book first introduces Verilog HDL and then uses it to design synchronous sequential machines and alternative synchronous sequential machines. Next, the text describes the synthesis of asynchronous sequential machines using Verilog HDL, and provides synthesis examples of pulse-mode asynchronous sequential machines using Verilog HDL.
Joseph Cavanagh is an adjunct professor in the Computer Engineering Department at Santa Clara University, California, USA. He is the author of several textbooks, including Computer Arithmetic and Verilog HDL Fundamentals (2009), Digital Design and Verilog HDL Fundamentals (2008), Verilog HDL: Digital Design and Modeling (2007), and Sequential Logic: Analysis and Synthesis (2006), as well as a novel, The Computer Conspiracy.
Introduction to Verilog HDL. Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL. Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL. Synthesis of Asynchronous Sequential Machines Using Verilog HDL. Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL. Appendices.
